application note mk5025 daisy chain dma introduction the sgs-thomson mk5025 x.25 link level controller is a vlsi device which provides a com- plete link level data communication control con- forming to the 1984 ccitt version of x.25. the mk5025 also supports x.32 (xid) and x.75 as well as single channel lapd for isdn with its ui frames and extended addressing capabilities. purpose although the mk5025 data sheet and technical manual provide detailed timing diagrams that spe- cifiy the relationships of the host interface sig- nals to one another for the sole requestor dma configuration, the designer may find it helpful to know the timing for the mk5025 as an element in a dma daisy chain. the purpose of this applica- tion brief is to provide a description of the mk5025 host interface in a daisy chain configura- tion, and some suggestions on how to implement the daisy chain. it should be also be noted that although the tim- ing diagrams in this document are provided to fa- cilitate the design process, the timing require- ments in the data sheet must still be met to ensure proper operation. daisy chain operation the daisy c hain operation of the mk5025 is se- lected by setting the bcon bit of csr4 so that pins 15, 16, and 17 are redefined as byte, busako, and busrq respectively. in the daisy chain mode the mk5025 dma opera- tion is still the same in that it still requests the bus by asserting hold/ busrq (pin 17), but it will not do so unless both busrq and hlda are inactive (de-asserted). also, the granting of the bus to the mk5025 should still consist of asserting hlda (pin 19) as indicated in the timing diagrams in the technical manual. however, if the mk5025 re- ceives hlda when it is not requesting the bus, the busako output (pin 16) will be driven low. AN491/0592 busrq hlda[1] busako[1] (hlda[2]) busako[2] (hlda[3]) busako[n-1] (hlda[n]) <35 ns <35 ns td figure 1: daisy chain bus master timing 1/5
additionally, if hlda is still asserted after busrq is deasserted by the mk5025, then the busako output will be driven low until hlda is deas- serted. figure 1 provides the typical timing rela- tionships for this mode of operation. as can be seen in this diagram, there is a possi- bility of the busako output being asserted at the end of a dma cycle from the time busrq is deasserted until hlda is deasserted. this pulse will not cause any problems unless it is delayed (by propagating through a large daisy chain) such that td (shown in figure 1) is sufficiently long to allow an oportunity to request the bus and see this pulse as a hlda acknowledging the bus re- quest. suggested daisy chain configuration in order to resolve the possibility of a problem re- sulting from the propagation of the end of dma cycle busako pulse, it is suggested that a daisy chain arragement such as that shown in figure 2 or 3 be used for daisy chains of more than 2 mk5025 devices. in the arrangement shown in figure 2, a latch is added to the end of the daisy chain for the purpose of latching busrq low (as- serted) until busako has propagated through the daisy chain. in this manner another mk5025 will not request the bus until busako has propa- gated through the entire chain, resetting the latch and allowing busrq to go inactive. it should be noted that the output of the latch drives the en- able of a tri-statable inverter to avoid contention on busrq. the solution suggested in figure 2 could of course also be implemented with a pld device such as an sgs-thomson gal 20v8. the pld device should be programmed such that it busrq hlda busako busrq hlda busako busrq hlda busako busrq hlda busako vcc hlda from host or bus arbiter vcc busrq to host mk5025[1] mk5025[2] mk5025[3] mk5025[n-1] mk5025[n] vcc vcc vcc vcc figure 3: round-robin daisy chain configuration busrq hlda busako busrq hlda busako busrq hlda busako busrq hlda busako vcc hlda from host or bus arbiter vcc busrq to host mk5025[1] mk5025[2] mk5025[3] mk5025[n-1] mk5025[n] figure 2: suggested daisy chain configuration application note 2/5
implements the following set of conditions: if busrq=0 latch busrq=0 and hlda=0 if busako[n]=0 release busrq where busako[n] is from the last device in the daisy chain. with this configuration the bus will typically be relenquished by the daisy chain in between each mk5025 bus master cycle or burst. the excep- tion to this is when two or more mk5025 devices request the bus simultaneously, in which case the devices would each obtain the bus in order of pri- ority as bus acknowledgement ( hlda to busako) propagates through the daisy chain. a variation to the suggested daisy chain operation is shown in figure 3. to each mk5025 there is added a pull-up resistor and a schottky diode in series with busrq. this allows each mk5025 in the chain to request the bus regardless of whether or not another mk5025 has already re- quested or posseses the bus at the time. how- ever, each device will not get the bus until the bus acknoledgement ( hlda) is passed on to the next device in the chain (through busako). thus, in a round-robin fashion, each mk5025 gets an equal opportunity to obtain the bus, whereas in figure 2 the mk5025[1] has first priority, followed by mk5025[2], if both request the bus simultane- ously. the decision on which approach to use depends upon the task required of each mk5025 and the available bus bandwidth. if the figure 2 scheme is used, it would be prudent to place the devices operating at the higher data rates in the higher priority positions in the daisy chain. if the round- robin approach is used it is important to realize that once bus mastership is granted by the host, it is possible that the bus may not be relinquished until all devices in the chain have had at least one dma cycle of bus mastership. bus release operation in the daisy chain or sole requestor configuration the use of the bus release function may be use- ful to allow the designer to force the mk5025 to relinquish the bus prior to completeion of a dma burst. the bus release function is programmed by setting bit busr in csr4<06>. setting this bit causes pin 15 to be defined as busrel. the purpose of the busrel (pin 15) function is to al- low an orderly abort to a mk5025 dma burst after completion of the current bus transfer cycle. it is important to note that the mk5025 has pro- grammable burst size of 2 bytes, 16 bytes, or un- limited (typically 64-66 bytes), and that dma bursting is only used for transfers of received and transmitted data. all buffer management func- tions are performed by the mk5025 using single word dma cycles. this includes reading the in- itialization block, updating the status buffer, man- aging the descriptor rings, etc. although the mk5025 does support transmission and reception of odd-byte frames (mcnt, mes- sage byte count may be odd), it is important to note that it does only word wide dma transfers (no single byte transfers). it is because of this that the mk5025 requires that all data structures (in- cluding bcnt, buffer byte count) and buffers be word aligned. therefore the byte, bm0 and bm1 signals are never used by the mk5025 to in- dicate single upper or lower byte transfers. so there should be no concern about redefining these pins as busako and busrel. from the timing diagrams in figure 4, it should be seen that busrel must be asserted at least 100 ns prior the rising edge of as (or falling edge of ale) in order for busrel to be recognized within that dma cycle. busrel can be deasserted co- incident with the rising edge of as. if busrel is asserted too late to be recognized within in the current dma cycle, then it should be held as- serted (or be re-asserted at least 100 ns prior) to the rising edge of as of the following dma cycle, in order for that cycle to be the last in the burst. conclusion the mk5025 offers great flexibility to the data communications system designer. the on-chip protocol processing may be used to save the de- signer much time in implementing standard proto- cols such as x.25, lapb, isdn lapd, x.32, and x.75, and the daisy chain information with associ- ated timing diagrams are provided to further facili- tate the design process. application note 3/5
busrq hlda as busrel > 100 ns > 0 ns t brel note: the t setup time must be met in order for busrel to be recognized within that dma cycle (causing the dma burst to end on that cycle). brel the dma burst will continue if busrel timing is not met figure 4: bus release timing application note 4/5
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics as sumes no responsibi lity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. spec ifications men- tioned in this publication are subject to ch ange without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical c omponents in life support devi ces or systems wi thout ex- press written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies aust ralia - brazil - france - germany - hong kong - i taly - japan - korea - malay sia - malta - morocco - the netherlands - s ingapore - spain - sweden - switzerland - taiwan - thaliand - united k ingdom - u.s.a. application note 5/5
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